Who Checks the Checker? Enhancing Component-level Architectural SEU Fault Tolerance for End-to-End SoC Protection

TL;DR

This paper proposes a combined fault-tolerance approach for SoC components, including interconnect and voting logic, to enhance SEU resilience with minimal overhead, demonstrated on a RISC-V microcontroller.

Contribution

It introduces an overlap-based method to protect both components and interconnections, improving end-to-end SEU fault tolerance with reduced area overhead.

Findings

Achieves over 99.9% fault tolerance in RTL and netlist.

Demonstrates 22% lower overhead compared to single global methods.

Validates approach through simulation-based fault injection and physical implementation.

Abstract

Single-event upset (SEU) fault tolerance for systems-on-chip (SoCs) in radiation-heavy environments is often addressed by architectural fault-tolerance approaches protecting individual SoC components (e.g., cores, memories) in isolation. However, the protection of voting logic and interconnections among components is also critical, as these become single points of failure in the design. We investigate combining multiple fault-tolerance approaches targeting individual SoC components, including interconnect and voting logic to ensure end-to-end SoC-level architectural SEU fault tolerance, while minimizing implementation area overheads. Enforcing an overlap between the protection methods ensures hardening of the whole design without gaps, while curtailing overheads. We demonstrate our approach on a RISC-V microcontroller SoC. SEU fault-tolerance is assessed with simulation-based fault injection. Overheads are assessed with full physical implementation. Tolerance to over 99.9% of faults in both RTL and implemented netlist is demonstrated. Furthermore, the design exhibits 22% lower implementation overhead compared to a single global fault-tolerance method, such as fine-grained triplication.