Per-Bank Memory Bandwidth Regulation for Predictable and Performant Real-Time System

TL;DR

This paper introduces a per-bank memory bandwidth regulation approach for multicore SoCs, improving predictability and performance by addressing DRAM bank-level interference.

Contribution

It presents a novel bank-aware memory regulation technique implemented on an open-source RISC-V SoC, demonstrating significant throughput gains and better isolation.

Findings

Per-bank regulation mitigates bank contention effectively.

Achieves 5.74x throughput improvement over traditional methods.

Maintains performance isolation for real-time workloads.

Abstract

Modern multicore system-on-chips (SoCs) share off-chip DRAM across cores, where bank-level interference can significantly degrade performance and threaten real-time guarantees. While prior work has focused on per-core bandwidth regulation, these approaches treat main memory as a monolithic resource and overlook DRAM's inherent bank-level parallelism. We show that DRAM interference is fundamentally a bank-level phenomenon. We characterize the guaranteed bandwidth of modern DRAM, demonstrate that it remains effectively constant across generations, and show how this limitation can be exploited by single-bank attacks. These results highlight the need for bank-aware memory management for predictable and efficient real-time systems. We design and implement a novel per-bank memory bandwidth regulator in an open-source RISC-V SoC and evaluate it using FireSim with both synthetic and real-world workloads. Our evaluation demonstrates that per-bank regulation effectively mitigates adversarial bank contention and achieves a 5.74x average throughput improvement for best-effort workloads over traditional bank-oblivious approaches while providing the same-level of performance isolation guarantees for real-time workloads.