Generalizable Verilog Modeling Framework for Synchronous and Asynchronous Superconducting Pulse-Based Logic Gates

TL;DR

This paper introduces a Verilog-based modeling framework for superconducting SFQ logic gates that supports both synchronous and asynchronous designs, enabling functional and timing verification with SDF compatibility.

Contribution

It is the first framework to support both synchronous and asynchronous SFQ gates in Verilog, facilitating scalable modeling and verification of superconducting logic circuits.

Findings

Validated models through device-level simulations showing correct functionality.

Demonstrated timing constraint coverage and compatibility with SDF back annotation.

RTL simulation of mixed synchronous-asynchronous circuits proved framework utility.

Abstract

Superconducting Single Flux Quantum (SFQ) logic offers a promising platform for ultra-low-power, high-frequency computing. However, their pulse-based nature poses challenges for scalable modeling, design, and verification using conventional hardware description languages (HDLs), which are designed for level-based digital logic. Prior efforts have required complex Verilog support modules to enable Standard Delay Format (SDF) compatibility and have provided limited coverage of SFQ cell types. This work presents a Verilog-based modeling framework for SFQ gates that enables functional and timing verification while maintaining compatibility with Standard Delay Format (SDF) back annotation and is the first framework to support both synchronous and asynchronous SFQ gates. The proposed models are validated through device-level simulations, demonstrating correct functionality and timing constraint coverage. RTL simulation of mixed synchronous-asynchronous circuits further demonstrate the utility of the proposed framework.