High-yield integration design of fixed-frequency superconducting qubit systems using siZZle-CZ gates

TL;DR

This paper introduces the siZZle-CZ gate, a scalable and collision-robust method for fixed-frequency superconducting qubits that enables high-fidelity operations and high fabrication yield in large quantum processors.

Contribution

It presents the siZZle-CZ gate, which relaxes drive frequency restrictions, allowing scalable lattice architectures with high yield despite fabrication-induced frequency variations.

Findings

Supported >99.6% CZ fidelities across broad parameters

Achieved 80% and 100% zero-collision yields in square and heavy-hex lattices

Demonstrated scalability to >1000 qubits with high yield

Abstract

Fixed-frequency transmon qubits, characterized by simple architectures and long coherence times, are promising platforms for large-scale quantum computing. However, the rapidly increasing frequency collisions, which directly reduce the fabrication yield, hinder scaling, especially in cross-resonance (CR) gate-based architectures, wherein the restricted drive frequency severely limits the available design space. We investigate the Stark-induced ZZ by level excursions (siZZle) gate, which relaxes this limitation by allowing arbitrary drive-frequency choices. Extensive numerical analyses across a broad parameter range -- including the far-detuned regime that has received negligible prior attention -- reveal wide operating windows that support controlled-Z (CZ) fidelities >99.6%. Leveraging these windows, we design lattice architectures containing >1000 qubits, showing that even under 0.25% fabrication-induced frequency dispersion, the zero-collision yields in square and heavy-hexagonal lattices reach 80% and 100%, respectively. Thus, the siZZle-CZ gate is a scalable and collision-robust alternative to the CR gate, offering a viable route toward high-yield fixed-frequency transmon quantum processors.