Gate-Drain Leakage Enhanced by Drain-Induced Dielectric Barrier Lowering in Gate-All-Around Field Effect Transistors

TL;DR

This paper investigates the leakage mechanisms in GAAFETs, revealing that drain-induced dielectric barrier lowering significantly enhances gate-to-drain tunneling leakage at negative gate voltages, impacting device scaling.

Contribution

It provides first-principles simulations identifying drain-induced dielectric barrier lowering as a key factor in leakage, guiding future device optimization.

Findings

Leakage at negative gate voltages is due to gate-to-drain tunneling.

Drain-induced dielectric barrier lowering enhances leakage.

Radiation-induced defects have limited impact at positive gate voltages.

Abstract

Gate-All-Around Field-Effect Transistors (GAAFETs), now entering high-volume production as successors to fin field-effect transistor technology, are enabling continued scaling and enhanced performance in advanced semiconductor nodes. However, the drain-current in GAAFETs strongly deviates from the thermionic dependence at negative gate voltages, exhibiting the existence of leakage that is additionally enhanced at high applied biases. Understanding the origin of this leakage is essential for determining the scaling limits of GAAFETs and for guiding device and material optimizations aimed at suppressing the off-state current. Additionally, recent experimental measurements have revealed the increased influence of radiation-induced defects in the negative gate voltage regime, with their impact remaining largely negligible for positive gate voltages. Through predictive first-principles simulations, we demonstrate that the observed leakage current at negative gate voltages originates from gate-to-drain tunneling, which is significantly enhanced by drain-induced dielectric barrier lowering between the gate and drain.