Quantifying Gate Contribution in Quantum Feature Maps for Scalable Circuit Optimization

TL;DR

This paper introduces GATE, a method to optimize quantum feature maps by assessing gate significance, leading to smaller, faster circuits that maintain or improve classification accuracy across various quantum hardware scenarios.

Contribution

The paper presents a novel gate significance index for quantum circuit optimization, applicable to both simulators and real hardware, enhancing scalability and performance in quantum machine learning.

Findings

Reduces circuit size and runtime without sacrificing accuracy

Effective across noise-free, noisy, and real hardware environments

Intermediate threshold levels often yield optimal trade-offs

Abstract

Quantum machine learning offers promising advantages for classification tasks, but noise, decoherence, and connectivity constraints in current devices continue to limit the efficient execution of feature map-based circuits. Gate Assessment and Threshold Evaluation (GATE) is presented as a circuit optimization methodology that reduces quantum feature maps using a novel gate significance index. This index quantifies the relevance of each gate by combining fidelity, entanglement, and sensitivity. It is formulated for both simulator/emulator environments, where quantum states are accessible, and for real hardware, where these quantities are estimated from measurement results and auxiliary circuits. The approach iteratively scans a threshold range, eliminates low-contribution gates, generates optimized quantum machine learning models, and ranks them based on accuracy, runtime, and a balanced performance criterion before final testing. The methodology is evaluated on real-world classification datasets using two representative quantum machine learning models, PegasosQSVM and Quantum Neural Network, in three execution scenarios: noise-free simulation, noisy emulation derived from an IBM backend, and real IBM quantum hardware. The structural impact of gate removal in feature maps is examined, compatibility with noise-mitigation techniques is studied, and the scalability of index computation is evaluated using approaches based on density matrices, matrix product states, tensor networks, and real-world devices. The results show consistent reductions in circuit size and runtime and, in many cases, preserved or improved predictive accuracy, with the best trade-offs typically occurring at intermediate thresholds rather than in the baseline circuits or in those compressed more aggressively.