Mitigating the Bandwidth Wall via Data-Streaming System-Accelerator Co-Design

TL;DR

This paper presents a co-designed system and accelerator for transformer inference that significantly improves throughput by optimizing data streaming and compute-transfer overlap, addressing bandwidth limitations in hardware acceleration.

Contribution

It introduces MatrixFlow, a systolic-array accelerator with a novel page-aligned matrix multiplication, and Gem5-AcceSys, a simulation platform for exploring system integration, jointly optimizing transformer inference performance.

Findings

Up to 22x speedup over CPU baseline

5x to 8x improvements over existing accelerators

Achieves 80% of on-device HBM performance with PCIe host memory

Abstract

Transformers have revolutionized AI in natural language processing and computer vision, but their large computation and memory demands pose major challenges for hardware acceleration. In practice, end-to-end throughput is often limited by paged data movement and interconnect bandwidth rather than raw MAC count. This work proposes a unified system-accelerator co-design approach for transformer inference that jointly optimizes a matrix accelerator and its system integration through paged streaming dataflows and explicit overlap of compute and transfer. On the hardware side, we introduce MatrixFlow, a loosely coupled 16x16 systolic-array accelerator with a page-aligned block matrix multiplication method using 4 KB tiles, a small on-chip buffer of about 20 KB, and a pipelined schedule of DMA, compute, and DMA-out to utilize interconnect bandwidth efficiently. On the system side, we develop Gem5-AcceSys, an extension of the gem5 full-system simulator that explores standard interconnects such as PCIe and configurable memory hierarchies including Direct Memory, Direct Cache, and Device Memory modes with SMMU/TLB effects. We evaluate the co-design using gem5 simulations on representative transformer models including BERT and ViT across multiple data types and system setups. Results show up to 22x end-to-end speedup over a CPU-only baseline and 5x to 8x gains over state-of-the-art loosely and tightly coupled accelerators. We further show that a standard PCIe-based host-memory design can achieve about 80 percent of the performance of on-device HBM. Overall, paged streaming and pipeline overlap, rather than large local SRAMs, are the most effective levers for efficient transformer inference under realistic system constraints.