Controller Datapath Aware Verification of Masked Hardware Generated via High Level Synthesis
Nilotpola Sarma, Vaishali Ghanshyam Chaudhuri, and Chandan Karfa

TL;DR
This paper presents MaskedHLSVerif, a formal verification tool for HLS-generated masked cryptographic hardware, effectively reducing false positives caused by resource sharing and ensuring security against Power Side Channel Attacks.
Contribution
It introduces a novel verification strategy tailored for HLS-generated masked hardware, addressing false positives and security flaws caused by HLS optimizations.
Findings
Successfully verifies cryptographic benchmarks with cascaded masked gadgets
Detects masking flaws induced by HLS optimizations
Reduces false positives compared to existing tools like REBECCA
Abstract
Masking is a countermeasure against Power Side Channel Attacks (PSCAs) in both software and hardware implementations of cryptographic algorithms. Compared to software masking, implementing masked hardware is time consuming and error prone. Recent approaches, therefore, rely on High Level Synthesis (HLS) tools to automatically generate masked Register Transfer Level (RTL) hardware from verified masked software, significantly reducing design effort. Since HLS was never developed for security, HLS optimizations may impact PSCA security of the generated RTL. As a result, verifying the PSCA security of HLS generated masked RTL is crucial. Existing hardware masking verification tools can verify masked hardware, but may produce false positives when applied to HLS generated designs with controller datapath architectures obtained due to resource-shared datapath obtained via HLS. This work…
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Taxonomy
TopicsCryptographic Implementations and Security · Security and Verification in Computing · Physical Unclonable Functions (PUFs) and Hardware Security
