Quantifying Memory Cells Vulnerability for DRAM Security

TL;DR

This paper presents a detailed circuit-level framework to quantify DRAM cell vulnerabilities, linking physical charge leakage and disturbance effects to security-related properties like retention, integrity, and confidentiality.

Contribution

It introduces a novel quantitative model connecting physical DRAM behaviors to security vulnerabilities, enabling systematic evaluation of cell-level risks.

Findings

Vulnerability patterns are non-uniform and context-dependent.

The framework links device physics to security properties.

Practical tools for security evaluation of DRAM are developed.

Abstract

Dynamic Random Access Memory (DRAM) is pervasive in computer systems. Cell vulnerabilities caused by unintended phenomena (forced retention failure, latency alteration, rowhammer and rowpress) lead to unintended bit flips in memory. These phenomena have been explored as attacks to violate data integrity and confidentiality during normal operation, but also exploited as a benefit in security systems as a method to generate random secret keys and unique device fingerprints (e.g. Physically Unclonable Functions). In both cases, attackers may wish to exploit knowledge of individual cell flip vulnerability to predict the current/future data contents of a set of cells, which can be utilised to break security systems. In this work, we develop a quantitative, cell-level circuit framework that models DRAM vulnerability directly from its physical charge leakage and disturbance pathways. By linking these device-layer behaviours to system-level security properties, our framework enables systematic evaluation of DRAM with respect to volatility (retention), integrity (disturbance-induced modification), and confidentiality (pattern-dependent leakage). We further demonstrate how the framework can be applied to well-known failure modes, revealing non-uniform and context-dependent vulnerability patterns. This work provides both theoretical foundations and practical evaluation tools for evaluating the suitability of DRAM use within security applications.