An FPGA-Based SoC Architecture with a RISC-V Controller for Energy-Efficient Temporal-Coding Spiking Neural Networks

TL;DR

This paper presents an FPGA-based SoC architecture with a RISC-V controller designed for energy-efficient temporal-coding SNNs, achieving significant memory reduction and low-latency inference suitable for edge AI applications.

Contribution

It introduces a compact, fully FPGA-implemented SoC architecture for temporal-coding SNNs, integrating novel event-driven processing techniques and a RISC-V controller for improved efficiency and scalability.

Findings

Achieves up to 16x memory reduction for weights.

Runs fully on Xilinx Artix-7 FPGA with low latency.

Maintains high accuracy of 97.0% on MNIST.

Abstract

Spiking Neural Networks (SNNs) offer high energy efficiency and event-driven computation, ideal for low-power edge AI. Their hardware implementation on FPGAs, however, faces challenges due to heavy computation, large memory use, and limited flexibility. This paper proposes a compact System-on-Chip (SoC) architecture for temporal-coding SNNs, integrating a RISC-V controller with an event-driven SNN core. It replaces multipliers with bitwise operations using binarized weights, includes a spike-time sorter for active spikes, and skips noninformative events to reduce computation. The architecture runs fully on a Xilinx Artix-7 FPGA, achieving up to 16x memory reduction for weights and lowering computational overhead and latency, with 97.0% accuracy on MNIST and 88.3% on FashionMNIST. This self-contained design provides an efficient, scalable platform for real-time neuromorphic inference at the edge.