General circuit compilation protocol into partially fault-tolerant quantum computing architecture

TL;DR

This paper introduces a new circuit execution protocol for the STAR quantum architecture that efficiently implements continuous non-Clifford gates using probabilistic resource states and joint measurements, reducing time overhead.

Contribution

It proposes a novel protocol employing parallel resource state creation and QUBO-based optimization to improve efficiency in fault-tolerant quantum circuit execution.

Findings

Protocol reduces time overhead through parallel trials and optimization.

Performance estimators accurately predict execution time and optimal topology.

Efficient implementation of continuous gates in fault-tolerant quantum computing.

Abstract

As we are entering an early-FTQC era, circuit execution protocols with logical qubits and certain error-correcting codes are being discussed. Here, we propose a circuit execution protocol for the space-time efficient analog rotation (STAR) architecture. Gate operations within the STAR architecture is based on lattice surgery with surface codes, but it allows direct execution of continuous gates $Rz(\theta)$ as non-Clifford gates instead of $T = Rz(\pi/4)$. $Rz(\theta)$ operations involve creation of resource states $|m_\theta \rangle = \frac{1}{\sqrt{2}} (|0 \rangle + e^{i\theta} |1\rangle ) $ followed by ZZ joint measurements with target logical qubits. While employing $Rz(\theta)$ enables more efficient circuit execution, both their creations and joint measurements are probabilistic processes and adopt repeat-until-success (RUS) protocols which are likely to result in considerable time overhead. Our circuit execution protocol aims to reduce such time overhead by parallel trials of resource state creations and more frequent trials of joint measurements. By employing quadratic unconstrained binary optimization (QUBO) in determining resource state allocations within the space, we successfully make our protocol efficient. Furthermore, we proposed performance estimators given the target circuit and qubit topology. It successfully predicts the time performance within less time than actual simulations do, and helps find the optimal qubit topology to run the target circuits efficiently.