SYMDIREC: A Neuro-Symbolic Divide-Retrieve-Conquer Framework for Enhanced RTL Synthesis and Summarization

TL;DR

SYMDIREC is a neuro-symbolic framework that improves RTL synthesis and summarization by decomposing tasks into symbolic subgoals, retrieving relevant code, and assembling verified outputs, outperforming existing prompting methods.

Contribution

It introduces a novel neuro-symbolic approach that incorporates symbolic planning into LLM-based RTL synthesis and summarization without requiring LLM fine-tuning.

Findings

~20% higher Pass@1 rates for synthesis

15-20% ROUGE-L improvements for summarization

Effective across Verilog and VHDL without fine-tuning

Abstract

Register-Transfer Level (RTL) synthesis and summarization are central to hardware design automation but remain challenging for Large Language Models (LLMs) due to rigid HDL syntax, limited supervision, and weak alignment with natural language. Existing prompting and retrieval-augmented generation (RAG) methods have not incorporated symbolic planning, limiting their structural precision. We introduce SYMDIREC, a neuro-symbolic framework that decomposes RTL tasks into symbolic subgoals, retrieves relevant code via a fine-tuned retriever, and assembles verified outputs through LLM reasoning. Supporting both Verilog and VHDL without LLM fine-tuning, SYMDIREC achieves ~20% higher Pass@1 rates for synthesis and 15-20% ROUGE-L improvements for summarization over prompting and RAG baselines, demonstrating the benefits of symbolic guidance in RTL tasks.