ETM2: Empowering Traditional Memory Bandwidth Regulation using ETM

TL;DR

ETM2 leverages Arm's ETM component to create a portable, hardware-assisted memory bandwidth regulator that improves real-time multicore system performance by reducing memory interference.

Contribution

This work repurposes the ETM for memory bandwidth regulation, offering a minimal-software, portable solution that outperforms previous methods like MemGuard and MemPol.

Findings

ETM2 effectively enforces per-core memory bandwidth regulation.

ETM2 demonstrates scalability across various Arm boards.

It enables new regulation options previously infeasible.

Abstract

The Embedded Trace Macrocell (ETM) is a standard component of Arm's CoreSight architecture, present in a wide range of platforms and primarily designed for tracing and debugging. In this work, we demonstrate that it can be repurposed to implement a novel hardware-assisted memory bandwidth regulator, providing a portable and effective solution to mitigate memory interference in real-time multicore systems. ETM2 requires minimal software intervention and bridges the gap between the fine-grained microsecond resolution of MemPol and the portability and reaction time of interrupt-based solutions, such as MemGuard. We assess the effectiveness and portability of our design with an evaluation on a large number of 64-bit Arm boards, and we compare ETM2 with previous works using a setup based on the San Diego Vision Benchmark Suite on the AMD Zynq UltraScale+. Our results show the scalability of the approach and highlight the design trade-offs it enables. ETM2 is effective in enforcing per-core memory bandwidth regulation and unlocks new regulation options that were infeasible under MemGuard and MemPol.