A Scalable Open-Source QEC System with Sub-Microsecond Decoding-Feedback Latency

TL;DR

This paper presents an open-source, integrated quantum error correction system built on RISC-V architecture, achieving sub-microsecond decoding-feedback latency suitable for large-scale quantum computers.

Contribution

It introduces a fully integrated hardware platform with real-time control, scalable architecture, and low-latency decoding, advancing practical fault-tolerant quantum computing.

Findings

End-to-end latency of 446 ns for a distance-3 surface code

Scalable architecture capable of sub-microsecond latency for a distance-21 surface code

Demonstrated integration of control, communication, and decoding subsystems

Abstract

Quantum error correction (QEC) is essential for realizing large-scale, fault-tolerant quantum computation, yet its practical implementation remains a major engineering challenge. In particular, QEC demands precise real-time control of a large number of qubits and low-latency, high-throughput and accurate decoding of error syndromes. While most prior work has focused primarily on decoder design, the overall performance of any QEC system depends critically on all its subsystems including control, communication, and decoding, as well as their integration. To address this challenge, we present an open-source, fully integrated QEC system built on RISC-Q, a generator for RISC-V-based quantum control architectures. Implemented on RFSoC FPGAs, our system prototype integrates real-time qubit control, a scalable distributed multi-board architecture, and the state-of-the-art hardware QEC decoder within a low-latency, high-throughput decoding pipeline, forming a complete hardware platform ready for deployment with superconducting qubits. Experimental evaluation on a three-board prototype based on AMD ZCU216 RFSoCs demonstrates an end-to-end QEC decoding-feedback latency of 446 ns for a distance-3 surface code, including syndrome aggregation, network communication, syndrome decoding, and error distribution. Extrapolating from measured subsystem performance and state-of-the-art decoder benchmarks, the architecture can achieve sub-microsecond decoding-feedback latency up to a distance-21 surface code ($\sim$881 physical qubits) when scaled to larger hardware configurations.