Optimization of the HHL Algorithm

TL;DR

This paper explores practical optimization strategies for the HHL quantum algorithm, focusing on improving fidelity and scalability for different matrix structures on near-term quantum simulators.

Contribution

It introduces and evaluates two optimization techniques—Suzuki-Trotter decomposition and block encoding—for enhancing HHL performance based on matrix sparsity and structure.

Findings

HHL achieves high fidelity for structured matrices but struggles with dense ones.

Block encoding improves fidelity for moderately dense matrices.

Trotterisation is effective for sparse systems, reducing qubit requirements.

Abstract

The Harrow-Hassidim-Lloyd (HHL) algorithm is a quantum algorithm for solving systems of linear equations that, in principle, offers an exponential improvement in scaling with the system size compared to classical approaches. In this work, we investigate the practical implementation and optimisation of the HHL algorithm with a focus on improving its performance on near-term quantum simulators. After outlining the algorithm, we examine two optimisation strategies aimed at improving fidelity and scalability: Suzuki-Trotter decomposition of the Hamiltonian evolution operator and a block-encoding approach that embeds the problem matrix into a larger unitary operator. The performance of these methods is evaluated through simulations on matrices with varying sparsity, including diagonal, tridiagonal, moderately dense, and fully dense cases. Our results show that while HHL achieves near-ideal fidelity for highly structured matrices, performance degrades as sparsity decreases due to the increasing cost of Hamiltonian simulation and reduced post-selection probability due to higher condition number. Block encoding is found to provide improved fidelity for moderately dense matrices, whereas Trotterisation offers a qubit-efficient approach for sparse systems. These results highlight the importance of matrix structure in determining the practical efficiency of HHL and inform future implementations that combine algorithmic optimisation with hardware-aware design.