bitSMM: A bit-Serial Matrix Multiplication Accelerator

TL;DR

bitSMM is a flexible, power-efficient FPGA and ASIC accelerator for neural network inference on spacecraft, supporting configurable precision and optimized for space constraints.

Contribution

The paper introduces bitSMM, a novel bit-serial matrix multiplication accelerator with configurable precision, designed specifically for space applications with power and reliability constraints.

Findings

Achieves up to 19.2 GOPS on FPGA.

Reaches 73.22 GOPS in ASIC implementation.

Offers high energy efficiency with 2.973 GOPS/W on FPGA.

Abstract

Neural-network (NN) inference is increasingly present on-board spacecraft to reduce downlink bandwidth and enable timely decision making. However, the power and reliability constraints of space missions limit the applicability of many state-of-the-art NN accelerators. This paper presents bitSMM, a bit-serial matrix multiplication accelerator built around a systolic array of bit-serial multiply--accumulate (MAC) units. The design supports runtime-configurable operand precision from 1 to 16 bits and evaluates two MAC variants: a Booth-inspired architecture and a standard binary multiplication with correction architecture. We implement bitSMM in [System]Verilog and evaluate it on an AMD ZCU104 FPGA and through ASIC physical implementation using the asap7 and nangate45 process design kits. On the FPGA, bitSMM achieves up to 19.2~GOPS and 2.973~GOPS/W, and in asap7 it achieves up to 73.22~GOPS, 552~GOPS/mm$^2$, and 40.8~GOPS/W.