Evaluating Calibration-Based Digital Twins for IBM Quantum Hardware Simulation

TL;DR

This paper assesses the accuracy of calibration-based digital twins for IBM Quantum hardware by comparing their simulation results with actual device measurements, highlighting the importance of device-specific validation.

Contribution

It introduces a workflow for building digital twins from calibration data and evaluates their effectiveness across different IBM QPUs and circuit depths.

Findings

Calibration-based twins often closely match hardware outcomes.

Backend-derived twins are practical and competitive baselines.

Agreement varies with device and transpilation settings.

Abstract

We evaluate calibration-based digital twins for IBM Quantum hardware, aiming to reproduce hardware measurement outcomes on classical simulators. We present a workflow that builds twins from downloadable calibration CSV files by mapping coherence times, gate and readout error rates, and operation durations to thermal-relaxation, depolarizing, and readout error channels, while reconstructing a directed coupling map to restore connectivity constraints during transpilation. We compare four twin variants (CSV-built, backend-derived simulator, backend-derived noise model, and fake-backend snapshots) under a common execution and validation protocol. Experiments on two IBM QPUs, ibm_brisbane and ibm_sherbrooke, use randomized five-qubit circuits of depths 10, 20, and 30 across four optimization levels. Weighted Jaccard similarity indicates that twins constructed from downloadable calibration CSV data often achieved the closest agreement with hardware, while backend-derived twins provided competitive and practical baselines. The results further show that agreement depends on both the target device and the transpilation settings, underscoring the need to validate digital twins for the specific execution setup rather than assuming transferability across devices.