Exploiting temporal parallelism for LSTM Autoencoder acceleration on FPGA

TL;DR

This paper presents a novel FPGA-based accelerator that exploits temporal parallelism to enable concurrent multi-layer processing of LSTM autoencoders, achieving significant speedups and energy efficiency for real-time anomaly detection.

Contribution

The paper introduces a dataflow FPGA architecture that leverages temporal parallelism for multi-layer LSTM processing, surpassing prior single-layer optimization approaches.

Findings

Latency speedup up to 79.6x over CPU

Energy reduction up to 1722x compared to CPU

Superior scalability for deeper networks

Abstract

Recurrent Neural Networks (RNNs) are vital for sequential data processing. Long Short-Term Memory Autoencoders (LSTM-AEs) are particularly effective for unsupervised anomaly detection in time-series data. However, inherent sequential dependencies limit parallel computation. While previous work has explored FPGA-based acceleration for LSTM networks, efforts have typically focused on optimizing a single LSTM layer at a time. We introduce a novel FPGA-based accelerator using a dataflow architecture that exploits temporal parallelism for concurrent multi-layer processing of different timesteps within sequences. Experimental evaluations on four representative LSTM-AE models with varying widths and depths, implemented on a Zynq UltraScale+ MPSoC FPGA, demonstrate significant advantages over CPU (Intel Xeon Gold 5218R) and GPU (NVIDIA V100) implementations. Our accelerator achieves latency speedups up to 79.6x vs. CPU and 18.2x vs. GPU, alongside energy-per-timestep reductions of up to 1722x vs. CPU and 59.3x vs. GPU. These results, including superior network depth scalability, highlight our approach's potential for high-performance, real-time, power-efficient LSTM-AE-based anomaly detection on FPGAs.