An Extended Study of Gear-Ratio-Aware Standard Cell Layout Generation for DTCO Exploration

TL;DR

This paper introduces CPCell, a flexible standard-cell layout generation framework that optimizes layout quality and scalability for advanced nodes by supporting arbitrary gear ratios and offsets through co-optimization techniques.

Contribution

The paper presents a novel framework for gear-ratio-aware cell layout generation that enhances layout quality and scalability using layered grid graphs and constraint programming.

Findings

Layout quality improved via Middle-of-Line routing and pin accessibility constraints.

Supports netlists with up to 48 transistors efficiently.

Quantifies impact of gear ratio choices on PPA and IR-drop.

Abstract

Advanced nodes decouple contacted poly pitch (CPP) and lower-metal pitch to improve routability. We present CPCell, an efficient standard-cell layout generation framework, to support arbitrary gear ratio (GR) and offset parameters through a fine-grained layered grid graph and constraint-programming-based placement-routing co-optimization. Layout quality is improved via Middle-of-Line routing, M0 pin enablement, pin accessibility constraints and a weighted multi-objective formulation that jointly optimizes cell layouts. To scale to netlists with up to 48 transistors, we incorporate acceleration techniques including transistor clustering, identical transistor partitioning, routing lower bound tightening and early termination strategies. Comprehensive cell-level and block-level studies are conducted to evaluate GR and offset choices, quantify the benefits of the proposed objectives and assess their impact on power, performance, area and IR-drop outcomes.