CellE: Automated Standard Cell Library Extension via Equality Saturation

TL;DR

CellE is a formal framework that uses equality saturation to automatically extend standard cell libraries, significantly improving area and delay in VLSI design.

Contribution

It introduces CellE, a novel equality saturation-based method for exhaustive discovery of functionally equivalent subcircuits for library extension.

Findings

Achieves 15.41% average area reduction

Up to 23.64% area reduction over prior work

Demonstrates 8.00% average delay reduction in commercial flow

Abstract

Automated standard cell library extension is crucial for maximizing Quality of Results (QoR) in modern VLSI design. We introduce CellE, a novel framework that leverages formal methods to achieve exhaustive discovery of functionally equivalent subcircuits. CellE applies equality saturation to the post-mapping netlist, generating an e-graph to cluster all functionally equivalent implementations. This canonical representation enables an efficient pattern mining algorithm to select the most area-optimal standard cells. Experimental results show a 15.41% average area reduction (up to 23.64% over prior work). Furthermore, characterization in a commercial flow demonstrates an 8.00% average delay reduction, confirming CellE's superior QoR optimization capabilities.