System-Technology Co-Optimization of Bitline Routing and Bonding Pathways in Monolithic 3D DRAM Architectures

TL;DR

This paper presents a co-optimization approach for bitline routing and bonding pathways in monolithic 3D DRAM, significantly improving density, speed, and energy efficiency through innovative architecture and device integration.

Contribution

It introduces a novel co-optimization methodology for 3D DRAM architecture, achieving higher density and performance with integrated device and routing design.

Findings

Achieved 2.6 Gb/mm^2 density, ~6x scaling over 2D DRAM.

Reduced row cycle time to 10.5 ns from 21.3 ns.

Lowered read/write energy by 60%.

Abstract

3D DRAM has emerged as a promising approach for continued density scaling, but its viability is limited by routing and hybrid bonding constraints to periphery, which may degrade sensing margin, latency, and array efficiency. With device characteristics and array parasitics extracted from TCAD, SPICE simulations are performed with peri logic in a CMOS-Bonded-Array (CBA). The analysis shows that the bitline strap architecture with amorphous oxide semiconductor (AOS) selectors is essential to manage routing congestion and parasitics. The optimized design achieves a bit density of 2.6 Gb/mm^2 (137 layers with Si access transistors or 87 layers with AOS), representing ~6x density scaling over D1b 2D DRAM. The design further demonstrates a nominal row cycle time (tRC) of 10.5 ns, compared to 21.3 ns in D1b, and a 60% reduction in read/write energy.