Distributed Quantum Computing via Adaptive Circuit Knitting

TL;DR

This paper introduces an Adaptive Circuit Knitting method that efficiently partitions large quantum circuits, significantly reducing sampling overheads for distributed quantum computing on multiple QPUs.

Contribution

The paper presents a novel adaptive partitioning technique that minimizes entanglement regions, enabling more efficient distributed quantum simulations without high-fidelity interconnects.

Findings

Reduced sampling overheads by up to four orders of magnitude.

Successfully simulated up to 60 qubits in disordered Ising models.

Parallel GPU implementation enhances simulation efficiency.

Abstract

Distributing quantum workloads over many Quantum Processing Units (QPUs) is a crucial step in scaling up quantum computers toward practical quantum advantage due to the limitations in size of a single QPU. In the absence of high-fidelity quantum interconnects, circuit knitting could provide a path to computing certain properties of large quantum systems on many QPUs of limited size in a distributed fashion using only classical communication. Circuit knitting partitions large quantum circuits into manageable sub-circuits, however, reconstructing observables in a straightforward manner comes at an exponential cost in sampling and classical post-processing. To mitigate the overhead this technique incurs, we introduce an Adaptive Circuit Knitting (ACK) method that finds efficient partitions of quantum circuits by discovering regions of minimal entanglement between subsystems. We simulate 1D and 2D disordered mixed-field Ising models up to 60 qubits and show that the ACK approach can reduce circuit knitting sampling overheads by up to four orders of magnitude for observables of interest. We highlight our parallel GPU-accelerated implementation and discuss the need for efficient classical simulators to enable distributed quantum algorithm development. Our techniques could enable efficient distribution of quantum simulation for both near-term and fault-tolerant architectures.