Explicit Block Encodings of Discrete Laplacians with Mixed Boundary Conditions

TL;DR

This paper introduces a unified quantum circuit framework for efficiently block encoding finite-difference Laplacian discretizations with mixed boundary conditions across arbitrary dimensions, improving gate efficiency and flexibility.

Contribution

It develops a versatile, modular quantum circuit construction for Laplacian operators with various boundary conditions and grid sizes, surpassing previous methods in efficiency and scope.

Findings

Lower gate counts in quantum circuits for Laplacian operators.

Higher success probabilities in quantum circuit benchmarks.

Supports mixed boundary conditions and anisotropic discretizations.

Abstract

Discrete Laplacian operators arise ubiquitously in scientific computing and frequently appear in quantum algorithms for tasks such as linear algebra, Hamiltonian simulation, and partial differential equations. Block encoding provides the standard method for accessing matrix data within quantum circuits. Efficient implementations of such algorithms require efficient block encodings of the discretized operator. While several general-purpose techniques exist for block encoding arbitrary matrices, they usually require deep quantum circuits. Moreover, existing efficient constructions that exploit Laplacian structure are limited in scope, typically assuming fixed boundary conditions or uniform grid resolutions. In this work, we present a unified framework for efficiently block encoding finite-difference discretizations of the Laplacian that supports Dirichlet, periodic, and Neumann boundary conditions in arbitrary spatial dimensions. Our construction allows different boundary conditions and grid sizes to be specified independently along each coordinate axis, enabling mixed-boundary and anisotropic discretizations within a single modular circuit architecture. We provide analytical gate-complexity estimates and perform circuit-level benchmarks after transpilation to an IBM hardware gate set. Across one-, two-, and three-dimensional examples, the resulting circuits exhibit substantially lower gate counts and higher success probabilities when compared to certain existing approaches.