SNAP-V: A RISC-V SoC with Configurable Neuromorphic Acceleration for Small-Scale Spiking Neural Networks

TL;DR

SNAP-V introduces a RISC-V-based neuromorphic SoC with configurable accelerators optimized for small-scale SNN inference, achieving high energy efficiency and accuracy suitable for edge computing.

Contribution

The paper presents a novel RISC-V neuromorphic SoC with two accelerator variants tailored for small-scale SNNs, combining energy efficiency with accurate inference.

Findings

Average accuracy deviation of 2.62% across configurations

Synaptic energy consumption of 1.05 pJ per SOP in 45 nm CMOS

Close agreement between software and hardware inference results

Abstract

Spiking Neural Networks (SNNs) have gained significant attention in edge computing due to their low power consumption and computational efficiency. However, existing implementations either use conventional System on Chip (SoC) architectures that suffer from memory-processor bottlenecks, or large-scale neuromorphic hardware that is inefficient and wasteful for small-scale SNN applications. This work presents SNAP-V, a RISC-V-based neuromorphic SoC with two accelerator variants: Cerebra-S (bus-based) and Cerebra-H (Network-on-Chip (NoC)-based) which are optimized for small-scale SNN inference, integrating a RISC-V core for management tasks, with both accelerators featuring parallel processing nodes and distributed memory. Experimental results show close agreement between software and hardware inference, with an average accuracy deviation of 2.62% across multiple network configurations, and an average synaptic energy of 1.05 pJ per synaptic operation (SOP) in 45 nm CMOS technology. These results show that the proposed solution enables accurate, energy-efficient SNN inference suitable for real-time edge applications.