Implementing and Optimizing an Open-Source SD-card Host Controller for RISC-V SoCs

TL;DR

This paper presents an optimized open-source SD card host controller integrated into a RISC-V SoC, significantly improving storage throughput for embedded Linux systems by addressing memory model bottlenecks.

Contribution

The authors developed an OS-compatible SD host controller for RISC-V SoCs, optimizing driver interactions to enhance performance and approaching interface throughput limits.

Findings

Achieved up to 11.1 MB/s throughput, close to SD interface limit.

Reduced performance bottleneck caused by RISC-V memory model.

Provided up to 6.5 times higher throughput than SPI-based storage.

Abstract

Recent announcements have shown the viability of end-to-end open-source (OS) Linux-capable RISC-V systems on chip (SoCs). However, practical application and software development platforms require efficient non-volatile storage, which is not adequately served by common SPI-based interfaces due to their limited throughput. Secure Digital (SD) cards are the de facto standard storage medium for embedded Linux systems; efficient SD host controller (SDHC) integration is thus essential for open-source RISC-V platforms. We present an OS SD host controller interface (SDHCI) peripheral integrated into the end-to-end OS Cheshire RISC-V SoC platform. The controller and its software stack are designed with full awareness of CVA6's memory system and Linux driver behavior; during evaluation, we identify a significant performance bottleneck caused by the RISC-V memory model and CVA6's implementation of the fence instruction, which flushes the pipeline and data cache on memory-mapped register accesses when cache management operations (CMOs) are unavailable. By customizing the driver's register access paths and avoiding unnecessary fences, we substantially reduced this overhead. Our fully OS controller achieves up to 11.1 MB/s throughput, approaching the 12.5 MB/s limit of the SD interface and providing up to 6.5 times the throughput of SPI-based storage.