Link Quality Aware Pathfinding for Chiplet Interconnects

TL;DR

This paper introduces a link pathfinding approach for chiplet interconnects that considers error correction overheads to meet strict bit error rate targets, optimizing link selection in chiplet systems.

Contribution

It develops a flow integrating RTL-based power and area estimates with ECC-aware link evaluation and a CP-SAT-based optimization for inter-chiplet link assignment.

Findings

ECC significantly impacts link performance comparisons.

CRC+ARQ reduces RS code strength needed at moderate BERs.

The proposed method effectively meets BER and bandwidth constraints.

Abstract

As chiplet-based integration advances, designers must select among short-reach die-to-die interconnect technologies with widely varying shoreline and areal bandwidth density, energy per bit, reach, and raw bit error rate (BER). Meeting stringent delivered BER targets in chiplet systems requires error-correcting codes (ECC), but incurs energy, area, and throughput overheads. We develop a flow centered around RTL synthesis power and area estimations to support pathfinding of inter-chiplet links under a stringent 10-27 delivered BER target. We synthesize a parameterized Reed-Solomon code with CRC-64 and Go-Back-N retry logic to estimate the correction overhead for different transceiver bit error rates. Results show that ECC can materially change link comparisons under common figures of merit and that CRC+ARQ can reduce the required RS strength (and decoder overhead) at moderate BERs while still meeting stringent delivered-BER targets. We present a CP-SAT-based link assignment formulation that uses these ECC-corrected metrics under reach, delivered-bandwidth, and shoreline constraints in system-level optimization.