VeriHGN: Heterogeneous Graph-Based Congestion Prediction for Chip Layout Verification

TL;DR

VeriHGN introduces a heterogeneous graph-based framework for more accurate early-stage congestion prediction in chip layout verification, reducing time and costs in VLSI design validation.

Contribution

It unifies circuit components and spatial layout into a single relational graph, improving congestion prediction accuracy over prior loosely coupled models.

Findings

Consistent improvements over state-of-the-art in prediction accuracy.

Effective on industrial benchmarks like ISPD2015 and CircuitNet datasets.

Enhances early-stage congestion estimation to reduce routing iterations.

Abstract

As Very Large Scale Integration (VLSI) designs continue to scale in size and complexity, layout verification has become a central challenge in modern Electronic Design Automation (EDA) workflows. In practice, congestion can only be accurately identified after detailed routing, making traditional verification both time-consuming and costly. Learning-based approaches have therefore been explored to enable early-stage congestion prediction and reduce routing iterations. However, although prior methods incorporate both netlist connectivity and layout features, they often model the two in a loosely coupled manner and primarily produce numerical congestion estimates. We propose VeriHGN, a verification framework built on an enhanced heterogeneous graph that unifies circuit components and spatial grids into a single relational representation, enabling more faithful modeling of the interaction between logical intent and physical realization. Experiments on industrial benchmarks, including ISPD2015, CircuitNet-N14, and CircuitNet-N28, demonstrate consistent improvements over state-of-the-art methods in prediction accuracy and correlation metrics.