Reducing Quantum Error Mitigation Bias Using Verifiable Benchmark Circuits
Joseph Harris, Kevin Lively, Peter Schuhmacher

TL;DR
This paper introduces verifiable benchmark circuits to improve quantum error mitigation bias, leading to significant fidelity gains on large-scale quantum circuits through hardware-aware benchmarking and noise extrapolation techniques.
Contribution
It proposes a novel method for constructing verifiable benchmark circuits that mirror application noise profiles, enhancing bias mitigation in quantum error correction.
Findings
Achieved up to 15% fidelity improvement on 100-qubit circuits.
Demonstrated effectiveness of benchmarked-noise zero-noise extrapolation (bnZNE).
Outperformed standard ZNE in simulations and hardware experiments.
Abstract
We present a simple, malleable and low-overhead approach for improving generic biased quantum error mitigation (QEM) methods, achieving up to 15% fidelity improvements over standard QEM on 100-qubit circuits with up to 2000 entangling gates. We do so by constructing verifiable benchmark circuits which mirror the application circuit's native-gate structure and thus noise profile. These circuits can be used to benchmark and mitigate the bias of the underlying error mitigation method, requiring only the application circuit and hardware native gate set. We present two methods for generating benchmark circuits; one is agnostic to the target hardware at the expense of a small overhead of single-qubit gates, while the other is specific to the IBM superconducting hardware and has no gate overhead. As a corollary, we introduce benchmarked-noise zero-noise extrapolation (bnZNE) as a simple…
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Taxonomy
TopicsQuantum Computing Algorithms and Architecture · Quantum Information and Cryptography · Quantum and electron transport phenomena
