Field Free Novel Architecture for Spintronic Flash Analog to Digital Converter

TL;DR

This paper introduces a novel, field-free spintronic flash ADC architecture using SOT MTJs that achieves high speed and low power consumption by innovative set switching techniques.

Contribution

It proposes a new architecture that eliminates the reset step in spintronic ADCs, enhancing speed and efficiency with dummy set utilization.

Findings

Power consumption of 476 μW

Conversion rate of 304.1 MHz

Field-free operation achieved

Abstract

A 3 bit Analog to Digital Converter (ADC) is designed using perpendicular Spin Orbit Torque Magnetic Tunnel Junction (SOT MTJ). A sampled analog input signal is transmitted as a spin orbit torque current (Iin) to a perpendicular SOT MTJ, and deterministic switching is supported by the Voltage Controlled Magnetic Anisotropy (VCMA) and Spin Transfer Torque (STT) switching methods. Analog to digital conversion is done by comparing input signal with varied critical current of SOT MTJs. The critical current of each is SOT MTJ governed by varying widths of Heavy Metal (HM). In the 3 bit ADC, there are two sets of 7 SOT MTJs for quantizing input value, a conversion set and dummy set for comparing the change in resistance state. As input signal passed through conversion set SOT MTJs switches from Parallel (P) to AntiParallel (AP) state if the input signal exceeds its critical current. The conversion set change in state is converted to thermometer codes by StrongARM latch comparator by comparing the resistance with dummy set SOT MTJs, where all the in P state or low resistance. A novel architecture is proposed for increasing speed of throughput, by utilizing the dummy set of as a conversion set and conversion set as dummy set, thus eliminating the reset step from analog to digital conversion. And by improving SOT-MTJ and timing blocks a field free spin flash ADC has a power consumption of 476 uW with a conversion rate of 304.1 MHz is produced.