Beyond Test-Time Training: Learning to Reason via Hardware-Efficient Optimal Control

TL;DR

This paper introduces a hardware-efficient optimal control layer for language models, enabling them to perform reasoning tasks more effectively by integrating planning mechanisms directly into their architecture.

Contribution

It proposes the Test-Time Control (TTC) layer that performs LQR planning within neural models, enhancing reasoning capabilities without extensive retraining.

Findings

Up to +27.8% performance on MATH-500

2-3x Pass@8 improvements on AMC and AIME

Efficient CUDA implementation for scalable inference

Abstract

Associative memory has long underpinned the design of sequential models. Beyond recall, humans reason by projecting future states and selecting goal-directed actions, a capability that modern language models increasingly require but do not natively encode. While prior work uses reinforcement learning or test-time training, planning remains external to the model architecture. We formulate reasoning as optimal control and introduce the Test-Time Control (TTC) layer, which performs finite-horizon LQR planning over latent states at inference time, represents a value function within neural architectures, and leverages it as the nested objective to enable planning before prediction. To ensure scalability, we derive a hardware-efficient LQR solver based on a symplectic formulation and implement it as a fused CUDA kernel, enabling parallel execution with minimal overhead. Integrated as an adapter into pretrained LLMs, TTC layers improve mathematical reasoning performance by up to +27.8% on MATH-500 and 2-3x Pass@8 improvements on AMC and AIME, demonstrating that embedding optimal control as an architectural component provides an effective and scalable mechanism for reasoning beyond test-time training.