Wrong Code, Right Structure: Learning Netlist Representations from Imperfect LLM-Generated RTL

TL;DR

This paper introduces a cost-effective framework that leverages imperfect LLM-generated RTL to learn netlist representations, enabling scalable circuit analysis despite limited high-quality labeled data.

Contribution

It presents a novel data augmentation approach using imperfect LLM-generated RTL to train netlist models, overcoming data scarcity in circuit representation learning.

Findings

Models trained on synthetic data perform well on real netlists.

The approach scales from operator-level to IP-level tasks.

Synthetic data can match or outperform high-quality labeled data.

Abstract

Learning effective netlist representations is fundamentally constrained by the scarcity of labeled datasets, as real designs are protected by Intellectual Property (IP) and costly to annotate. Existing work therefore focuses on small-scale circuits with clean labels, limiting scalability to realistic designs. Meanwhile, Large Language Models (LLMs) can generate Register-Transfer-Level (RTL) at scale, but their functional incorrectness has hindered their use in circuit analysis. In this work, we make a key observation: even when LLM-Generated RTL is functionally imperfect, the synthesized netlists still preserve structural patterns that are strongly indicative of the intended functionality. Building on this insight, we propose a cost-effective data augmentation and training framework that systematically exploits imperfect LLM-Generated RTL as training data for netlist representation learning, forming an end-to-end pipeline from automated code generation to downstream tasks. We conduct evaluations on circuit functional understanding tasks, including sub-circuit boundary identification and component classification, across benchmarks of increasing scales, extending the task scope from operator-level to IP-level. The evaluations demonstrate that models trained on our noisy synthetic corpus generalize well to real-world netlists, matching or even surpassing methods trained on scarce high-quality data and effectively breaking the data bottleneck in circuit representation learning.