Extension of ACETONE C code generator for multi-core architectures
Yanis A\"it-A\"issa, Thomas Carle (IRIT-TRACES), Sergei Chichin, Benjamin Lesage, Claire Pagetti

TL;DR
This paper extends the ACETONE C code generator to support multi-core architectures by defining a processor assignment problem, surveying existing solutions, and developing parallel code generation techniques.
Contribution
It introduces a formal processor assignment problem and proposes an extension to ACETONE for parallel code generation targeting multi-core systems.
Findings
Formal definition of processor assignment problem
Survey of existing parallel code generation solutions
Framework for evaluating worst-case execution time
Abstract
As the industry's interest in machine learning has grown in recent years, some solutions have emerged to safely embed them in safety-critical systems, such as the C code generator ACETONE. However, this framework is limited to generating sequential code, which cannot make most of the multi-core architectures. In this paper, we initiate an extension of ACETONE for the generation of parallel code by formally defining our processor assignment problem and surveying the state of the art on existing solutions. In the final paper, we will introduce the completed extension, including the implementation of the scheduling heuristic, the creation of templates implementing synchronization mechanisms, and an evaluation of the worst-case execution time of the framework's layers.
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Taxonomy
TopicsReal-Time Systems Scheduling · Embedded Systems Design Techniques · Parallel Computing and Optimization Techniques
