Architectural Design and Performance Analysis of FPGA based AI Accelerators: A Comprehensive Review
Soumita Chatterjee, Sudip Ghosh, Tamal Ghosh, Hafizur Rahaman

TL;DR
This comprehensive review discusses FPGA-based AI accelerators, highlighting their advantages, hardware optimizations, and current challenges to improve deep learning performance and energy efficiency.
Contribution
It provides an extensive overview of FPGA-based neural network accelerators, including hardware optimizations and challenges, advancing understanding of FPGA's role in AI hardware design.
Findings
FPGA accelerators offer flexible, high-efficiency solutions for deep learning.
Hardware optimizations like pipelining and quantization improve performance.
Identified challenges guide future FPGA-based AI accelerator development.
Abstract
Deep learning (DL) has emerged as a rapidly developing advanced technology, enabling the performance of complex tasks involving image recognition, natural language processing, and autonomous decision-making with high levels of accuracy. However, as these technologies evolve and strive to meet the growing demands of real-life applications, the complexity of DL models continues to increase. These models require processing of massive volumes of data, demanding substantial computational power and memory bandwidth. This gives rise to the critical need for hardware accelerators that can deliver both high performance and energy efficiency. Accelerator types include ASIC based solutions, GPU accelerators, and FPGA based implementations. The limitations of ASIC and GPU accelerators have led to FPGAs becoming one of the prominent solutions, offering distinct advantages for DL workloads. FPGAs…
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Taxonomy
TopicsEmbedded Systems Design Techniques · Advanced Neural Network Applications · Numerical Methods and Algorithms
