Measurement-Free Ancilla Recycling via Blind Reset: A Cross-Platform Study on Superconducting and Trapped-Ion Processors

TL;DR

This study evaluates a measurement-free ancilla recycling method called blind reset across superconducting and trapped-ion quantum processors, demonstrating significant latency reductions while maintaining high ancilla cleanliness.

Contribution

It introduces and experimentally validates a platform-calibrated blind reset technique for ancilla recycling, reducing cycle latency without compromising ancilla quality across different hardware platforms.

Findings

Blind reset reduces cycle latency by up to 38x.

Ancilla cleanliness remains above 0.84 at L=8.

Crossover lengths vary by platform, e.g., ~12 for IQM and ~11 for Rigetti.

Abstract

Ancilla reuse in repeated syndrome extraction couples reset quality to logical-cycle latency. We evaluate blind reset -- unitary-only recycling via scaled sequence replay -- on IQM Garnet, Rigetti Ankaa-3, and IonQ under matched seeds, sequence lengths, and shot budgets. Using ancilla cleanliness F_clean=P(|0>), per-cycle latency, and a distance-3 repetition-code logical-error proxy, platform-calibrated simulation identifies candidate regions where blind reset cuts cycle latency by up to 38x under NVQLink-class feedback overhead while maintaining F_clean >= 0.86 for L <= 6. Hardware experiments on IQM Garnet confirm blind-reset cleanliness >= 0.84 at L=8 (1024 shots, seed 42); platform-calibrated simulation for Rigetti Ankaa-3 predicts comparable performance. Architecture-dependent crossover lengths are L* ~ 12 (IQM), ~ 11 (Rigetti), ~ 1 (IonQ), and ~ 78 with GPU-linked external feedback. Two added analyses tighten deployment boundaries: a T1/T2 sensitivity map identifies coherence-ratio regimes, and error-bound validation confirms measured cleanliness remains consistent with the predicted diagnostic envelope. A deployment decision matrix translates these results into backend-specific policy selection.