AnalogToBi: Device-Level Analog Circuit Topology Generation via Bipartite Graph and Grammar Guided Decoding

TL;DR

AnalogToBi is a novel framework that generates device-level analog circuit topologies using bipartite graphs and grammar-guided decoding, achieving high validity and novelty without human-in-the-loop training.

Contribution

It introduces a bipartite graph representation, circuit-type conditioning, device renaming augmentation, and grammar-guided decoding to improve structural validity and generalization in topology generation.

Findings

Achieves high validity and novelty in circuit topology generation.

Effectively avoids memorization of training topologies.

Does not require human-in-the-loop training.

Abstract

Analog circuit design remains highly dependent on expert knowledge due to the complexity of device-level interactions and topology design. Recent transformer-based approaches for device-level topology generation have shown promise, yet they suffer from low electrical validity without human-in-the-loop (HITL) training and severe memorization caused by sequence-based circuit representations. In this work, we propose AnalogToBi, a framework for device-level analog circuit topology generation. AnalogToBi introduces circuit-type conditioning for categorizing heterogeneous multi-type topology datasets, device renaming augmentation to mitigate memorization, a bipartite graph representation for improved structural generalization, and grammar-guided decoding to enforce structural validity during bipartite graph generation. Experimental results demonstrate that AnalogToBi achieves high validity and novelty without HITL training while effectively avoiding memorization of training topologies. Our code is available at https://github.com/Seungmin0825/AnalogToBi.