SiliconMind-V1: Multi-Agent Distillation and Debug-Reasoning Workflows for Verilog Code Generation

TL;DR

SiliconMind-V1 introduces a multi-agent framework for Verilog code generation that combines reasoning, testing, and debugging, achieving higher correctness with fewer resources compared to existing methods.

Contribution

The paper presents a novel multi-agent approach for training data generation and verification in Verilog code synthesis, improving correctness and efficiency.

Findings

Outperforms state-of-the-art in functional correctness.

Uses fewer training resources.

Effective on multiple benchmark datasets.

Abstract

Large language models (LLMs) have recently emerged as a promising approach for automating Verilog code generation; however, existing methods primarily emphasize syntactic correctness and often rely on commercial models or external verification tools, which introduces concerns regarding cost, data privacy, and limited guarantees of functional correctness. This work proposes a unified multi-agent framework for reasoning-oriented training data generation with integrated testbench-driven verification, enabling locally fine-tuned LLMs, SiliconMind-V1, to iteratively generate, test, and debug Register-Transfer Level (RTL) designs through test-time scaling. Experimental results on representative benchmarks (VerilogEval-v2, RTLLM-v2, and CVDP) demonstrate that the proposed approach outperforms the state-of-the-art QiMeng-CodeV-R1 in functional correctness while using fewer training resources.