CktEvo: Repository-Level RTL Code Benchmark for Design Evolution
Zhengyuan Shi, Jingxin Wang, Tairan Cheng, Changran Xu, Weikang Qian, Qiang Xu

TL;DR
CktEvo introduces a repository-level RTL benchmark and framework that enables iterative, function-preserving PPA improvements across complete IP cores using LLMs and toolchain feedback.
Contribution
It provides the first repository-scale RTL benchmark with a closed-loop framework for LLM-assisted, cross-file, iterative RTL optimization.
Findings
Achieves PPA improvements without human intervention
Supports cross-file modifications in real-world RTL repositories
Establishes a foundation for LLM-assisted RTL design evolution
Abstract
Register-Transfer Level (RTL) coding is an iterative, repository-scale process in which Power, Performance, and Area (PPA) emerge from interactions across many files and the downstream toolchain. While large language models (LLMs) have recently been applied to hardware design, most efforts focus on generation or debugging from natural-language prompts, where ambiguity and hallucinations necessitate expert review. A separate line of work begins from formal inputs, yet typically optimizes high-level synthesis or isolated modules and remains decoupled from cross-file dependencies. In this work, we present CktEvo, a benchmark and reference framework for repo-level RTL evolution. Unlike prior benchmarks consisting of isolated snippets, our benchmark targets complete IP cores where PPA emerges from cross-file dependencies. Our benchmark packages several high-quality Verilog repositories from…
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Taxonomy
TopicsEmbedded Systems Design Techniques · Parallel Computing and Optimization Techniques · Formal Methods in Verification
