A Hybrid Residue Floating Numerical Architecture with Formal Error Bounds for High Throughput FPGA Computation

TL;DR

The paper introduces HRFNA, a novel hybrid residue floating point architecture for FPGAs that offers high throughput, predictable error bounds, and improved efficiency over traditional IEEE 754 FP32, suitable for scientific computing.

Contribution

It presents a formally defined hybrid residue floating point system with a complete FPGA microarchitecture, demonstrating significant performance and efficiency gains with bounded numerical errors.

Findings

Up to 2.4x higher throughput compared to FP32

38-55% LUT reduction

Up to 1.9x energy efficiency improvement

Abstract

Floating point arithmetic is costly on FPGA platforms due to wide datapaths, normalization, and carry propagation, motivating alternative numerical representations that improve throughput and efficiency. This paper presents the Hybrid Residue Floating Numerical Architecture (HRFNA), a fully specified numerical system that combines carry-free residue arithmetic with lightweight exponent-based scaling to achieve wide dynamic range, predictable error behavior, and efficient FPGA implementation. HRFNA is developed with a rigorous mathematical foundation: the hybrid number space is formally defined, correctness of arithmetic and normalization is proven, and explicit absolute and relative error bounds are derived, confining rounding to infrequent normalization events. A complete FPGA microarchitecture is presented, featuring deeply pipelined modular arithmetic, exponent management, and a CRT-based normalization engine that sustains an initiation interval of one cycle under steady-state operation. Application-level evaluation on dot products, dense matrix multiplication, and iterative Runge-Kutta ODE solvers demonstrates stable numerical behavior over long computation sequences. Implemented on a Xilinx Zynq UltraScale Plus ZCU104, HRFNA achieves up to 2.4 times higher throughput, 38 to 55 percent LUT reduction, and up to 1.9 times energy efficiency improvement compared to IEEE 754 FP32 baselines, while maintaining bounded numerical error. Comparative analysis shows that HRFNA occupies a previously unexplored design point between numerical stability, dynamic range, and hardware efficiency, making it well suited for FPGA-centric scientific and CAD-relevant computation.