A Compact XOR Gate Implemented With a Single Straintronic Magnetic Tunnel Junction

TL;DR

This paper introduces a highly compact, non-volatile XOR gate using a single straintronic magnetic tunnel junction, achieving low energy consumption and fast switching, suitable for advanced computing architectures.

Contribution

It presents the first design of an XOR gate with a single straintronic magnetic tunnel junction, significantly reducing footprint and energy compared to traditional transistor-based XOR gates.

Findings

Switching time ~200 ps

Energy dissipation ~225 aJ per operation

Order of magnitude lower energy than traditional XORs

Abstract

The XOR Boolean logic gate is widely used in many applications such as encryption (XOR ciphers), binary addition (half- and full-adders), error detection (parity bits), etc. but is challenging to construct because of its demanding conditional dynamics. It typically requires multiple logic switches or other types of gates, which results in a large gate footprint and low logic density. Here, we present the design of an XOR gate with a single straintronic magnetic tunnel junction which reduces the footprint dramatically. Such a gate is non-volatile and hence suitable for non-von-Neumann architectures, processor-in-memory, etc. The switching time of the gate is ~200 ps and the energy dissipation per gate operation is ~225 aJ. Cascading of successive stages is accomplished via a CMOS device which plays no role in the gate dynamics but is needed for gain to provide logic level restoration, fan-out and isolation between input and output. This 1 MTJ-1 CMOS design has an energy dissipation that is an order of magnitude smaller than what has been reported for traditional all-transistor XOR designs.