RISCBench: Benchmarking RISC-V Orchestration Efficiency in FPGA and FPGA-Like Computing Engines
Dave Ojika, Projjal Gupta, Preethi Budi, Herman Lam, Shreya Mehrotra

TL;DR
RISCBench introduces a benchmark suite and a new metric, SIT, to evaluate the sustained orchestration efficiency of RISC-V cores in heterogeneous FPGA-based systems, addressing a gap in existing performance metrics.
Contribution
The paper presents RISCBench and the SIT metric, providing a novel, platform-independent way to measure orchestration efficiency in heterogeneous RISC-V systems.
Findings
SIT captures sustained throughput beyond peak performance.
Synchronization and data residency impact realized throughput.
RISCBench effectively evaluates orchestration efficiency across platforms.
Abstract
Heterogeneous systems increasingly rely on RISC-V cores as orchestration engines to manage data movement, synchronization, and scheduling across accelerators and reconfigurable fabrics. Conventional performance metrics, such as FLOPs, TOPS/W, or energy per operation, do not capture orchestration efficiency, even though it often dictates sustained system behavior. This gap is increasingly relevant as systems evolve toward tightly coupled heterogeneous fabrics and co-packaged accelerators, where control-plane behavior determines whether these platforms achieve their promised performance. We present RISCBench, a kernel benchmark suite and open methodology for quantifying orchestration efficiency. RISCBench introduces the Sustained Instantaneous Throughput (SIT) metric, which accumulates instantaneous throughput over near-aggregate execution intervals, capturing sustained efficiency…
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Taxonomy
TopicsEmbedded Systems Design Techniques · Parallel Computing and Optimization Techniques · Software-Defined Networks and 5G
