NL2GDS: LLM-aided interface for Open Source Chip Design

TL;DR

NL2GDS is a novel framework that uses large language models to translate natural language descriptions into complete ASIC layouts, significantly reducing area, delay, and power consumption.

Contribution

It introduces a modular LLM-based pipeline for translating natural language into synthesizable RTL and GDSII layouts, integrating design intent capture, verification, and automated synthesis.

Findings

Up to 36% area reduction on benchmarks

35% delay reduction achieved

70% power savings demonstrated

Abstract

The growing complexity of hardware design and the widening gap between high-level specifications and register-transfer level (RTL) implementation hinder rapid prototyping and system design. We introduce NL2GDS (Natural Language to Layout), a novel framework that leverages large language models (LLMs) to translate natural language hardware descriptions into synthesizable RTL and complete GDSII layouts via the open-source OpenLane ASIC flow. NL2GDS employs a modular pipeline that captures informal design intent, generates HDL using multiple LLM engines and verifies them, and orchestrates automated synthesis and layout. Evaluations on ISCAS'85 and ISCAS'89 benchmark designs demonstrate up to 36% area reduction, 35% delay reduction, and 70% power savings compared to baseline designs, highlighting its potential to democratize ASIC design and accelerate hardware innovation.