Dissipation-Reliability Tradeoff for Stochastic CMOS Bits in Series

TL;DR

This paper investigates how chaining CMOS bits can improve error correction at low voltages, analyzing the tradeoff between reliability and energy dissipation using advanced numerical methods.

Contribution

It introduces a novel analysis of CMOS chain error suppression using tensor networks, revealing the reliability-dissipation tradeoff in low-voltage regimes.

Findings

Bit-flip error time scales exponentially with bias voltage.

CMOS chains provide enhanced stability over single units at low bias.

Increasing bias voltage reduces dissipation for the same stability.

Abstract

Physical instantiations of a bit of information are subject to thermal noise that can trigger unintended bit-flip errors. Bits implemented with CMOS technology typically operate in regimes that reliably suppress these errors with a large bias voltage, but miniaturization and circuit design for implantable biomedical devices motivate error suppression via alternative low-voltage strategies. We present and analyze an error-suppression technique that involves coupling multiple CMOS units into chains, introducing a natural error correction arising from inter-unit correlations. Using tensor networks to numerically solve a stochastic master equation for the CMOS chain, we quantify the reliability-dissipation tradeoff across system sizes that would be intractable with conventional sparse-matrix methods. The calculations show that the typical time for bit-flip errors scales exponentially with the bias voltage but subexponentially with the chain length. While a CMOS chain adds stability compared to a single CMOS unit for a fixed low bias voltage, increasing the bias voltage is a lower-dissipation route to equivalent stability.