Joint Hardware-Workload Co-Optimization for In-Memory Computing Accelerators

TL;DR

This paper introduces a co-optimization framework for designing in-memory computing accelerators that efficiently support multiple neural network workloads, balancing performance and generality through an evolutionary algorithm.

Contribution

It presents a novel joint hardware-workload co-optimization method that enhances the generality of IMC accelerators across diverse neural network models.

Findings

Achieves up to 76.2% EDAP reduction across 4 workloads.

Achieves up to 95.5% EDAP reduction across 9 workloads.

Demonstrates robustness on RRAM and SRAM-based architectures.

Abstract

Software-hardware co-design is essential for optimizing in-memory computing (IMC) hardware accelerators for neural networks. However, most existing optimization frameworks target a single workload, leading to highly specialized hardware designs that do not generalize well across models and applications. In contrast, practical deployment scenarios require a single IMC platform that can efficiently support multiple neural network workloads. This work presents a joint hardware-workload co-optimization framework based on an optimized evolutionary algorithm for designing generalized IMC accelerator architectures. By explicitly capturing cross-workload trade-offs rather than optimizing for a single model, the proposed approach significantly reduces the performance gap between workload-specific and generalized IMC designs. The framework is evaluated on both RRAM- and SRAM-based IMC architectures, demonstrating strong robustness and adaptability across diverse design scenarios. Compared to baseline methods, the optimized designs achieve energy-delay-area product (EDAP) reductions of up to 76.2% and 95.5% when optimizing across a small set (4 workloads) and a large set (9 workloads), respectively. The source code of the framework is available at https://github.com/OlgaKrestinskaya/JointHardwareWorkloadOptimizationIMC.