Agentic AI-based Coverage Closure for Formal Verification

TL;DR

This paper introduces an AI-driven workflow using Large Language Models to automate coverage analysis and gap identification in formal verification, significantly improving coverage metrics and verification efficiency in chip design.

Contribution

It presents a novel agentic AI-based framework that automates coverage closure tasks in formal verification, enhancing productivity and effectiveness over traditional methods.

Findings

Measurable increase in coverage metrics across designs

Coverage improvements correlate with design complexity

AI-driven approach accelerates verification process

Abstract

Coverage closure is a critical requirement in Integrated Chip (IC) development process and key metric for verification sign-off. However, traditional exhaustive approaches often fail to achieve full coverage within project timelines. This study presents an agentic AI-driven workflow that utilizes Large Language Model (LLM)-enabled Generative AI (GenAI) to automate coverage analysis for formal verification, identify coverage gaps, and generate the required formal properties. The framework accelerates verification efficiency by systematically addressing coverage holes. Benchmarking open-source and internal designs reveals a measurable increase in coverage metrics, with improvements correlated to the complexity of the design. Comparative analysis validates the effectiveness of this approach. These results highlight the potential of agentic AI-based techniques to improve formal verification productivity and support comprehensive coverage closure.