TinyIceNet: Low-Power SAR Sea Ice Segmentation for On-Board FPGA Inference

TL;DR

TinyIceNet is a low-power, FPGA-implemented neural network designed for real-time sea ice segmentation from Sentinel-1 SAR data, enabling efficient on-board processing for polar navigation.

Contribution

The paper introduces TinyIceNet, a novel compact neural network co-designed for FPGA deployment, optimized for low-power, real-time sea ice segmentation in spaceborne applications.

Findings

Achieves 75.216% F1 score on SOD segmentation

Reduces energy consumption by 2x compared to GPU baselines

Demonstrates near-real-time inference on FPGA

Abstract

Accurate sea ice mapping is essential for safe maritime navigation in polar regions, where rapidly changing ice conditions require timely and reliable information. While Sentinel-1 Synthetic Aperture Radar (SAR) provides high-resolution, all-weather observations of sea ice, conventional ground-based processing is limited by downlink bandwidth, latency, and energy costs associated with transmitting large volumes of raw data. On-board processing, enabled by dedicated inference chips integrated directly within the satellite payload, offers a transformative alternative by generating actionable sea ice products in orbit. In this context, we present TinyIceNet, a compact semantic segmentation network co-designed for on-board Stage of Development (SOD) mapping from dual-polarized Sentinel-1 SAR imagery under strict hardware and power constraints. Trained on the AI4Arctic dataset, TinyIceNet combines SAR-aware architectural simplifications with low-precision quantization to balance accuracy and efficiency. The model is synthesized using High-Level Synthesis and deployed on a Xilinx Zynq UltraScale+ FPGA platform, demonstrating near-real-time inference with significantly reduced energy consumption. Experimental results show that TinyIceNet achieves 75.216% F1 score on SOD segmentation while reducing energy consumption by 2x compared to full-precision GPU baselines, underscoring the potential of chip-level hardware-algorithm co-design for future spaceborne and edge AI systems.