Gate Stack Engineering for High-Mobility and Low-Noise SiMOS Quantum Devices

TL;DR

This study explores how materials engineering and device design influence mobility and charge noise in SiMOS quantum devices, highlighting pathways to optimize performance for scalable quantum computing.

Contribution

It provides a systematic experimental analysis linking gate-stack materials and processing conditions to mobility and noise, informing improved quantum device fabrication.

Findings

Higher ALD temperature improves mobility

HfO₂ enhances carrier mobility possibly via defect passivation

Poly-Si gates exhibit lowest charge noise

Abstract

We systematically investigate the interplay between materials engineering, quantum transport, and low-frequency charge noise in silicon metal--oxide--semiconductor (SiMOS) quantum devices. By combining Hall-bar transport measurements with charge-noise spectroscopy of gate-defined quantum dots, we identify correlations between gate-stack design, carrier mobility, and electrostatic noise, providing an experimental case study of material and process dependencies relevant to low-noise, high-mobility operation. Hall-bar studies reveal that increasing the atomic-layer-deposition temperature of Al$_2$O$_3$ markedly enhances mobility, whereas the choice of oxidant has little impact. Devices incorporating HfO$_2$ exhibit improved carrier mobility, an interesting observation that can plausibly be attributed to defect passivation associated with aluminum diffusion from the gate metal into the HfO$_2$ layer. Charge-noise measurements show a strong correlation between higher mobility and reduced noise, with TiPd-gated devices displaying both degraded transport and elevated charge noise. In contrast, the poly-Si-gated CMOS-foundry device achieves the lowest noise levels. Finally, dual-feedback dot--sensor stability mapping demonstrates enhanced charge stability in devices with the gate stacks studied here, underscoring their promise for scalable, high-fidelity silicon spin-qubit platforms.