Shifting in-DRAM

TL;DR

This paper introduces a novel in-DRAM bit-shifting architecture that enables efficient, bidirectional data shifts within DRAM subarrays without additional complex circuitry, improving in-memory computation capabilities.

Contribution

The paper proposes a new DRAM subarray design with extended migration cells that facilitate in-DRAM bit-shifting, maintaining compatibility with standard DRAM operations and eliminating the need for data transposition.

Findings

Operates on horizontally-stored data, avoiding data transposition overhead.

Maintains compatibility with standard DRAM operations.

Validated through timing, energy analysis, circuit simulation, and VLSI layout.

Abstract

Processing-in-Memory (PIM) architectures enable computation directly within DRAM and help combat the memory wall problem. Bit-shifting is a fundamental operation that enables PIM applications such as shift-and-add multiplication, adders using carry propagation, and Galois field arithmetic used in cryptography algorithms like AES and Reed-Solomon error correction codes. Existing approaches to in-DRAM shifting require adding dedicated shifter circuits beneath the sense amplifiers to enable horizontal data movement across adjacent bitlines or vertical data layouts which store operand bits along a bitline to implement shifts as row-copy operations. In this paper, we propose a novel DRAM subarray design that enables in-DRAM bit-shifting for open-bitline architectures. In this new design, we built upon prior work that introduced a new type of cell used for row migration in asymmetric subarrays, called a "migration cell". We repurpose and extend the functionality by adding a row of migration cells at the top and bottom of each subarray which enables bidirectional bit-shifting within any given row. This new design maintains compatibility with standard DRAM operations. Unlike previous approaches to shifting, our design operates on horizontally-stored data, eliminating the need and overhead of data transposition, and our design leverages the existing cell structures, eliminating the need for additional complex logic and circuitry. We present an evaluation of our design that includes timing and energy analysis using NVMain, circuit-level validation of the in-DRAM shift operation using LTSPICE, and a VLSI layout implementation in Cadence Virtuoso.