SAILOR: A Scalable and Energy-Efficient Ultra-Lightweight RISC-V for IoT Security

TL;DR

SAILOR introduces a modular, ultra-lightweight RISC-V core family optimized for IoT security, achieving significant improvements in energy efficiency and area reduction while maintaining high performance for cryptographic tasks.

Contribution

The paper presents a scalable, energy-efficient RISC-V core design with minimal area overhead, specifically tailored for cryptographic applications in IoT devices, addressing a gap in integrated security and efficiency.

Findings

Outperforms state-of-the-art in energy efficiency by up to 13x.

Reduces hardware area by up to 59%.

Maintains high performance with minimal overhead.

Abstract

Recently, RISC-V has contributed to the development of IoT devices, requiring architectures that balance energy efficiency, compact area, and integrated security. However, most recent RISC-V cores for IoT prioritize either area footprint or energy efficiency, while adding cryptographic support further compromises compactness. As a result, truly integrated architectures that simultaneously optimize efficiency and security remain largely unexplored, leaving constrained IoT environments vulnerable to performance and security trade-offs. In this paper, we introduce SAILOR, an energy-efficient and scalable ultra-lightweight RISC-V core family for cryptographic applications in IoT. Our design is modular and spans 1-, 2-, 4-, 8-, 16-, and 32-bit serialized execution data-paths, prioritizing minimal area. This modular design and adaptable data-path minimizes the overhead of integrating RISC-V cryptography extensions, achieving low hardware cost while significantly improving energy efficiency. We validate our design approach through a comprehensive analysis of area, energy, and efficiency trade-offs. The results surpass state-of-the-art solutions in both performance and energy efficiency by up to 13x and reduce area by up to 59 %, demonstrating that lightweight cryptographic features can be added without prohibitive overhead, and that energy- or area-efficient designs need not compromise performance.