Real-Time Stream Compaction for Sparse Machine Learning on FPGAs

TL;DR

This paper introduces a latency-optimized FPGA-based preprocessing method for sparse sensor data, enabling efficient Graph Neural Network acceleration in high-throughput, low-latency collider experiment triggers.

Contribution

It presents a hierarchical sparsity compression pipeline and an open-source hardware generator for FPGA-based preprocessing of sparse data, improving GNN hardware acceleration.

Findings

Achieved high throughput with minimal hardware utilization.

Demonstrated effective preprocessing in a GNN-based trigger for Belle II.

Evaluated scalability and resource efficiency across various parameters.

Abstract

Machine learning algorithms are being used more frequently in the first-level triggers in collider experiments, with Graph Neural Networks pushing the hardware requirements of FPGA-based triggers beyond the current state of the art. To meet the stringent demands of high-throughput and low-latency environments, we propose a concept for latency-optimized preprocessing of sparse sensor data, enabling efficient GNN hardware acceleration by removing dynamic input sparsity. Our approach rearranges data coming from a large number of First-In-First-Out interfaces, typically sensor frontends, to a smaller number of FIFO interfaces connected to a machine learning hardware accelerator. In order to achieve high throughput while minimizing the hardware utilization, we developed a hierarchical sparsity compression pipeline optimized for FPGAs. We implemented our concept in the Chisel design language as an open-source hardware generator. For demonstration, we implemented one configuration of our module as preprocessing stage in a GNN-based first-level trigger for the Electromagnetic Calorimeter inside the Belle II detector. Additionally we evaluate latency, throughput, resource utilization, and scalability for a wide range of parameters, to enable broader use for other large scale scientific experiments.