Low-Noise Quantum Dots in Ultra-Shallow Ge/SiGe Heterostructures for Prototyping Hybrid Semiconducting-Superconducting Devices

TL;DR

This study demonstrates that ultra-shallow Ge/SiGe heterostructures with thin SiGe caps can host low-noise quantum dots suitable for hybrid superconducting-semiconducting devices, with low charge noise comparable to deeper structures.

Contribution

The paper introduces a low-temperature fabrication process for ultra-shallow Ge/SiGe heterostructures with thin caps, enabling low-noise quantum dots compatible with superconducting integration.

Findings

Charge-noise level of 1.8 ± 1.0 μeV/√Hz in fabricated devices

Comparable noise performance to deeper heterostructures with high-temperature oxides

Potential for hybrid device prototyping with straightforward superconductor integration

Abstract

Planar germanium is currently the only semiconducting platform where high-coherence spin qubits and proximity-induced superconductivity have each been demonstrated. Recent research into spin qubits in Ge/SiGe heterostructures has focused on increasing the thickness of the SiGe capping layer, reporting improvements in the electrostatic noise levels. Meanwhile, heterostructures with thinner capping layers remain rather unexplored, despite the potential advantages for proximity-induced superconductivity. Here, we study a Ge/SiGe heterostructure with a thin SiGe cap $d \approx 4\ \mathrm{nm}$ and investigate its viability to host low-noise quantum dots. To keep the thermal budget compatible with superconducting layers, low-temperature oxide deposition processes were developed and implemented for the gate dielectrics. The charge-noise level of fabricated devices is estimated to be $1.8 \pm 1.0\ \mu\mathrm{eV}/\sqrt{\mathrm{Hz}}$, comparable to devices fabricated on shallow heterostructures $\left(d \sim 20\ \mathrm{nm}\right)$ with high-temperature deposited oxides. Low charge-noise levels, together with the straightforward integration of superconductors, make this heterostructure an attractive platform for prototyping hybrid semiconducting-superconducting devices.